A window-type ball grid array (WBGA) semiconductor package 1, as shown in FIG. 4, is a substrate-based structure in which a substrate 10 has an upper surface 100 and a lower surface 101 and is formed with an opening 102 penetrating through the same. A chip 11 is mounted via an adhesive 12 on the upper surface 100 of the substrate 10 in a face-down manner that, an active surface 110 of the chip 11 covers the opening 102 and partly exposed to the opening 102. A plurality of bonding wires 13 are formed through the opening 102 to electrically connect the partly-exposed active surface 110 of the chip 11 to the lower surface 101 of the substrate 10. Then, a molding process is performed to encapsulate the substrate 10 in a double-side manner that, an upper encapsulant 14 is formed on the upper surface 100 of the substrate 10 and encapsulates the chip 11, and a lower encapsulant 15 is formed on the lower surface 101 of the substrate 10 and encapsulates the opening 102 and bonding wires 13. Finally, a plurality of solder balls 16 are implanted on the lower surface 101 of the substrate 10 at area outside the lower encapsulant 15; this therefore completes fabrication of the WBGA semiconductor package 1.
A characteristic feature of the above window-type package structure 1 is to form the opening 102 through the substrate 10 for accommodating the bonding wires 13; this desirably shortens length of the bonding wires 13 and thus helps reduce overall package profile or thickness, such that electrical transmission or performances between the chip 11 and the substrate 10 can be efficiently implemented. During the molding process, an encapsulating mold, including an upper mold and a lower mold (not shown), is utilized; the upper and lower molds are designed in compliance with structural arrangement on the substrate 10 e.g. chip size, wire loops and substrate-opening size, so as to form appropriate upper and lower encapsulants 14, 15. The special mold design for fabricating the double-side molded structure would undesirably increase overall package fabrication costs.
In response to the above cost-increase problem, another conventional method for fabricating the WBGA semiconductor package 1′ is provided as described with reference to FIGS. 5A-5C. Referring to FIG. 5A, the first step is to perform chip-bonding and wire-bonding processes as above for a substrate 10 formed with an opening 102, allowing a chip 11 to be mounted over the opening 102 on an upper surface 100 of the substrate 10 and electrically connected to a lower surface 101 of the substrate 10 by a plurality of bonding wires 13 formed through the opening 102. Then, a printing process is performed to form a lower encapsulant 15 on the lower surface 101 of the substrate 10 for filling the opening 102 and encapsulating the bonding wires 13.
Referring to FIG. 5B, after fabrication of the lower encapsulant 15, a molding process is performed to form an upper encapsulant 14 on the upper surface 100 of the substrate 10 for encapsulating the chip 11.
Finally, referring to FIG. 5C, with a plurality of solder balls 16 being implanted on the lower surface 101 of the substrate 10 at area outside the lower encapsulant 15, fabrication of the semiconductor package 1′ is completed.
The printing technology utilized for forming the lower encapsulant 15 of the semiconductor package 1′ may be desirably more cost-effective to implement than the molding process as previously discussed. However, during the molding process for fabricating the upper encapsulant 14 (as shown in FIG. 5B), the chip 11 suffers different supports at positions corresponding to the lower encapsulant 15 and a lower mold of an encapsulating mold (not shown) that abuts against the lower surface 101 of the substrate 10 at area outside the lower encapsulant 15, such that cracks of the chip 11 may be easily caused by mold-flow impact from an encapsulating resin used for forming the upper encapsulant 14, thereby undesirably degrading reliability and yield of fabricated package products.
Accordingly, there is provided a further conventional method for fabricating the WBGA semiconductor package 1″ as described with reference to FIGS. 6A-6D. Referring to FIG. 6A, a substrate 10 formed with an opening 102 is mounted with a chip 11 via an adhesive 12 over the opening 102 on an upper surface 100 of the substrate 10. Then, a molding process is performed to form an upper encapsulant 14 on the upper surface 100 of the substrate 10 for encapsulating the chip 11.
Referring to FIG. 6B, after molding, a wire-bonding process is performed to form a plurality of bonding wires 13 for electrically connecting the chip 11 via the opening 102 to a lower surface 101 of the substrate 10.
Referring to FIG. 6C, a printing process is perform to form a lower encapsulant 15 on the lower surface 101 of the substrate 10 for filling the opening 102 and encapsulating the bonding wires 13.
Referring to FIG. 6D, finally, a plurality of solder balls 16 are implanted on the lower surface 101 of the substrate 10 at area outside the lower encapsulant 15, and thus, fabrication of the semiconductor package 1″ is completed.
As the upper encapsulant 14 (by molding) is formed prior to the lower encapsulant 15 (by printing), the unbalanced supporting problem for the chip 11 can be eliminated without causing cracks of the chip 11. However, with the molding process being carried out before forming the bonding wires 13, bond pads 111 of the chip 11 are exposed to the opening 102 (as shown in FIG. 6A) and easily subject to contamination during molding; this thereby adversely affects subsequent wire-bonding quality. Moreover, during the wire-bonding process for forming the bonding wires 13, the substrate 10 mounted with the chip 11 is turned upside down, allowing an active surface 110 of the chip 11 to be exposed via the opening 102 and bonded with the bonding wires 13. A wire-bonder (not shown) is employed to firstly form studs on the bond pads 111 situated on the exposed active surface 110 of the chip 11, and then to draw from the studs to form the bonding wires 13 to be connected to the lower surface 101 of the substrate 10. However, stud formation usually induces a strong force applied from the wire-bonder to the chip 11; since the adhesive 12 for attaching the chip 11 to the substrate 10 undergoes twice curing processes respectively during application of the adhesive 12 and during molding for forming the upper encapsulant 14 and is thus reduced with its cushion effect, delamination may easily occur at interface between the twice-cured adhesive 12 and the chip 11 in response to the strong force applied from the wire-bonder during stud formation; delamination may undesirably cause leakage problems during tests of the semiconductor package 1″.
Therefore, the problem to be solved herein is to provide a semiconductor package for preventing delamination and bond pad contamination as well as chip cracks, thereby assuring reliability and yield of fabricated package products.